Based on Intel® Core™ microarchitecture (formerly codenamed Haswell) and manufactured on 22-nanometer process technology, these processors provide significant performance over the previous-generation Intel Xeon processor E7 v2 product family. This is the first Intel® Xeon® processor product family that supports Intel® Transaction Synchronization Extensions (Intel® TSX).
For a more in-depth discussion of the key features and the architecture of the Intel® Xeon® E7 v3 product family see the technical overview document.
Key supported features you should be aware of, as a Software Developer:
- This product family introduces new instructions that are used to improve cryptographic processing performance. Please consult these articles that show how to optimize SHA512 and SHA256 cryptographic hash functions.
Intel® Advanced Vector Extensions 2 (Intel® AVX2) extends Intel® AVX by promoting most of the 128-bit SIMD integer instructions with 256-bit numeric processing capabilities. Many SSE2 instructions can be replaced by Intel AVX2 equivalents. Large-integer applications such as big data analytic will be benefit from Intel AVX2. In addition, Intel AVX2 provides enhanced functionality for broadcast/permute operations on data elements, vector shift instructions with variable-shift count per data element, and instructions to fetch non-contiguous data elements from memory. Introduces new instructions that are beneficial to high performance computing applications such as benchmark and database applications.
Intel TSX helps when application performance is hindered by lock contention problems. General information about Intel TSX can be found here. For more information about Intel TSX, see these articles: hardware lock elision and restricted transactional memory with older compilers, Intel® TSX profiling with Linux perf, monitoring Intel® TSX with Intel® PCM, adding lock elision to Linux and Intel TSX fall back. Also see a good case study about improving in-memory database with Intel® TSX.
- Cache Monitoring Technology (CMT) provides per-virtual-machine (VM) cache utilization information to the operating system (OS) or Virtual Machine Monitor (VMM) so that it can make better decisions on workload scheduling. An introduction about CMT can be found here. For more details about CMT, see these articles about its interface, usage and software support and tools.
- Intel® Virtual Machine Control Structure (Intel® VMCS) Shadowing works by reducing the frequency in which the guest virtual machine monitor (VMM) requires assistance from the parent VMM. Its goal is to eliminate the VM-exits due to VMREAD and VMWRITE instructions executed by the guest VMM. The Intel and Citrix collaboration article provides a good description about the benefit of using Intel® VMCS shadowing. A team at IBM® enabled this feature and gained significant performance improvement.
- New Reliability features include Enhanced Machine Check Architecture Generation 2 (eMCA2). Prior to eMCA2, errors were logged in architected registers and OS/VMM (Virtual Machine Management) was informed. This will restrict the platform firmware from doing fault diagnosis. eMCA2 allows errors (corrected and uncorrected) to first signal the BIOS/SMM(System Management Mode) before determining if the errors need to be informed to the OS/VMM . Another important reliability feature is Memory Address Range Mirroring (MARM). MARM allows the BIOS or OS to determine a range of memory addresses to be mirrored instead of mirroring the entire memory space. More information about these features can be found here.
Learn more about the Intel® Xeon® E7 v3 product family here. Also, these software vendors are already developed applications that are highly optimized to run Intel® Xeon® processor E7 v3 family server platform.
